Due to high performance requirements in modern computer technology, pluralities of integrated circuits are usually combined with functional units. These units may include up to hundreds of integrated circuits which are commonly placed next to each other on the surface of a substrate component. As there are numerous data signals to transfer from and to each integrated circuit, the substrate typically comprises a dense and complex interwiring structure. Additionally, this structure must be stable with respect to mechanical and thermal stresses since the temperature of the integrated circuits varies significantly due to their actual activity level.
One structure comprising the requisite properties is the well known multilayer ceramic substrate (MLC). This substrate type typically consists of alumina that is, in many cases, compounded with other components, e.g., glass. Usually the integrated circuit semiconductor devices attached to and in surface contact with the substrate consist of monocrystalline silicon with a thermal expansion coefficient of 2.5.times.10.sup.-6 per K. As alumina has a different expansion coefficient (5.8.times.10.sup.-6 per K), tension forces occur between substrate and the integrated device which may generate heat during operation of the device. Such heating of the device may result in shorter life times of the whole circuit/substrate unit. Therefore, standard MLC substrates require the use of stress reduction techniques, including effective cooling, limitation of chip size and specific connection techniques, e.g., controlled collapse chip connection (C4).
During MLC fabrication, different layers (carrying conduction lines for power distribution and signal transfer) are stacked to form a wiring network structure comprising a plurality of horizontal and vertical interconnections. To achieve a substrate of sufficient rigidity, the whole structure is `baked` in a sintering process. This high temperature step must be carefully controlled due to the fact that significant shrinking of the substrate typically occurs. The sintering operation must be performed so that each individual layer, including its numerous vias for vertical wirings, exactly maintains its geometry and orientation with respect to the other layers of the stacked structure. If sintering is not performed with precise uniformity, it may cause opens and/or shorts of internal conducting paths, e.g., by dislocations of the vertical contacting vias. This leads to non-recoverable defective MLC substrates, because such internal wiring faults can not be repaired.
The fabrication of modern MLC substrates requires a whole sequence of various high precision process steps, with operations performed early in the sequence often having an impact on operations performed later in the sequence. Due to these dependencies, the possibilities for reworking the MLC substrates are generally limited. Accordingly, each notable modification of the MLC layout, either in size or internal wiring design, causes outstanding and expensive changes in equipment and processes. In addition, the substitution or renewal of tooling frequently causes undesired alterations of parameters which can result in defective products. As rework in most cases is virtually impossible, these inherent difficulties in MLC production lead to substantial yield limitations.